1. Field of the Invention
The present invention relates to a charge transfer device and method for manufacturing the same, and more specifically to a charge transfer device of the two-layer electrode, two-phase drive type having charge storage regions and charge barrier regions formed in self-alignment with transfer electrodes, and a method for manufacturing the same.
2. Description of Related Art
At present, an image input device having a large number of pixels and a high degree of portability, such as a highly definition television camera and a digital still camera, is now actively developed.
For this image input device, it has become indispensable to develop a solid state image pickup device having a reduced power consumption. In particular, it has become a significant object to lower a drive voltage of a horizontal charge transfer section, which has a high drive frequency in the solid state image pickup device.
In general, the horizontal charge transfer section is constituted of a two-layer electrode, two-phase drive type charge transfer device, since it is necessary to transfer signal charges at a high speed.
Now, referring to FIGS. 1A to 1G, there are shown diagrammatic sectional views for illustrating a process for manufacturing the prior art two-layer electrode, two-phase drive type charge transfer device, which is disclosed in, for example, C. K. Kim, xe2x80x9cTWO-PHASE CHARGE COUPLED LINEAR IMAGING DEVICES WITH SELF-ALIGNED IMPLANTED BARRIERxe2x80x9d, IEDM Technical Digest, 1974, pp55-58 (the content of which is incorporated by reference in its entirety into this application) and Japanese Patent Application Pre-examination Publication No. JP-A-62-071273, (an English abstract of JP-A-62-071273 is available from the Japanese Patent Office and the content of the English abstract of JP-A-62-071273 is incorporated by reference in its entirety into this application).
First, as shown in FIG. 1A, at a principal surface of a P-type semiconductor substrate 101 such as a P-type silicon substrate having an impurity concentration of about 1xc3x971015 cmxe2x88x923, there is formed an N-type semiconductor region 102 having the conductivity opposite to that of the substrate and having an impurity concentration of about 1xc3x971017 cmxe2x88x923, and also having the depth of about 0.5 xcexcm from the principal surface of the P-type semiconductor substrate 101. By a thermal oxidation, a first insulator film 103 having a thickness of about 100 nm is formed on a surface of the an N-type semiconductor region 102.
Next, as shown in FIG. 1B, on the first insulator film 103, a plurality of first charge transfer electrodes . . . , 104i, 104j, 104k, 104l, . . . , (represented by 104) are formed of polysilicon by a low pressure CVD (chemical vapor deposition) process to have a thickness of about 300 nm and to be located with a predetermined intervals.
Succeedingly, after the first insulator film 103 is selectively removed by using the first charge transfer electrodes 104 as a mask, a thermal oxidation is carried out again so that, as shown in FIG. 1C, a second insulator film 105 having a thickness of about 100 nm is formed on the surface of the N-type semiconductor region 102, and a third insulator film 106 having a thickness of about 200 nm because of an enhanced oxidation of the polysilicon is formed on a top surface and a side surface of each of the first charge transfer electrodes 104. Alternatively, by the CVD process causing SiH4 gas and H2O gas to react, a second insulator film 105 having a thickness of about 100 nm is formed on the surface of the N-type semiconductor region 102, and a third insulator film 106 having a thickness of about 100 nm is formed on a top surface and a side surface of each of the first charge transfer electrodes 104.
Then, as shown in FIG. 1D, an impurity (for example, boron) of the conductivity opposite to that of the N-type semiconductor region 102 is selectively introduced using the first charge transfer electrodes 104 and the third insulator film 106 as a mask, by an ion-implantation having an incident angle of 0 (zero) degree, namely, perpendicular to the surface of the substrate, so that Nxe2x88x92xe2x88x92 semiconductor regions 108 having an impurity concentration of about 8xc3x971016 cmxe2x88x923 are formed in self-alignment with the first charge transfer electrodes 104 and the third insulator film 106.
Thereafter, as shown in FIG. 1E, on the second insulator film 105 and the third insulator film 106, a plurality of second charge transfer electrodes . . . , 109i, 109j, 109k, 109l, . . . , (represented by 109) are formed of polysilicon by the low pressure CVD process to have a thickness of about 300 nm, and located with a predetermined intervals. Each of the second charge transfer electrodes 109 is formed to cover the Nxe2x88x92xe2x88x92 semiconductor region 108 between each pair of adjacent first charge transfer electrodes 104, and to partially overlap on a near side end of each of the pair of adjacent first charge transfer electrodes 104.
Succeedingly, as shown in FIG. 1F, an interlayer insulator film 110 is formed to cover the whole. Then, not-shown through-holes are formed, and a not-shown aluminum film is deposited and patterned so that, as shown in FIG. 1G, a pair of metal interconnections 111-1 and 111-2 are alternately connected to transfer electrode pairs, each of which is composed of one first charge transfer electrode 104 (for example 104i) and one adjacent second charge transfer electrode 109 (for example 109i). In the shown example, transfer electrode pairs 104j+109j, 104l+109l are connected to the metal interconnections 111-1 and transfer electrode pairs 104i+109i, 104k+109kare connected to the metal interconnections 111-2.
In the above mentioned prior art charge transfer device of the two-layer electrode, two-phase drive type, signal charges can be transferred from the right to the left in the drawing, by driving the pair of metal interconnections 111-1 and 111-2 with a pair of transfer clock pulses xcfx861 and xcfx862 having the amplitude of about 5V and having the phase different from each other by 180 degrees as shown in FIG. 2, respectively.
However, the following problems have been encountered in the above mentioned prior art charge transfer device of the two-layer electrode, two-phase drive type. Since the N-type semiconductor region having the same impurity concentration is formed directly under the first charge transfer electrode and under the gap between the first charge transfer electrode and the second charge transfer electrode, in particular when it is attempted to transfer the signal charge with a low drive voltage (for example on the order of 3V), since the third insulator film 3 under the second charge transfer electrode in the area of the gap effectively acts as a thick insulator, a potential recess is easy to occur, and therefore, the transfer efficiency drops.
Referring to FIG. 3, there is shown a diagram for illustrating the problem of the above mentioned prior art charge transfer device of the two-layer electrode, two-phase drive type when the drive voltage is made low. In the diagram of FIG. 3, a potential diagram is combined with a sectional view of the charge transfer device in order to indicate a position in the coordinate. In addition, the dotted line indicates a potential diagram when the drive voltage is high (for example on the order of 5V) and the solid line indicates a potential diagram when the drive voltage is low (for example on the order of 3V).
The potential recess occurring due to the gap between the first transfer electrode and the second transfer electrode is modulated by a fringe electric field and therefore is suppressed, if a potential difference between portions directly under adjacent transfer electrodes is large. Namely, as shown in FIG. 3, when the drive voltage of the charge transfer device is sufficiently high (for example on the order of 5V in the prior art), and therefore, when the potential difference xcfx862 (xcfx8621, xcfx8622) is sufficiently large, the potential recess does not occur, and therefore, the signal charges are smoothly transferred.
On the other hand, if a potential difference between a portion directly under the first transfer electrode and a portion directly under an adjacent second transfer electrode becomes small, the potential recess becomes easy to occur, so that an inadequate transfer occurs. For example, as shown in FIG. 3, when the drive voltage of the charge transfer device is low (for example on the order of 3V in the prior art), and therefore, when the potential difference xcfx861 (xcfx8611, xcfx8612) is small, the potential difference xcfx8611 between the portion directly under the first transfer electrode and the portion directly under the adjacent second transfer electrode supplied with the same voltage as that applied to the first transfer electrode, becomes small, and the potential difference xcfx8612 between the portion directly under the first transfer electrode and the portion directly under the adjacent second transfer electrode supplied with the voltage different from that applied to the first the first transfer electrode, also becomes small. As a result, the recess xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d of potential occur under the gap of the first transfer electrode and the second transfer electrode adjacent to each other.
When the above mentioned potential recess occurs, not only the signal charge is trapped in the potential recess, but also the charge transfer electric field in the proximity of the potential recess becomes weak, with the result that the transfer of signal charge is dominantly carried out by the thermal diffusion, and therefore, the transfer time becomes very long. Accordingly, it becomes difficult to transfer the signal charge at a high speed, and the inadequate transfer becomes easy to occur.
Therefore, when the drive voltage of the charge transfer device is lowered, in order to perform the electric charge transfer with a high transfer efficiency and at a high speed, it is important to form the charge transfer device so as to minimize or prevent the above mentioned potential recess.
Accordingly, it is an object of the present invention to provide a charge transfer device and method for manufacturing the same, which have overcome the above mentioned defect of the conventional one.
Another object of the present invention is to provide a charge transfer device of the two-layer electrode, two-phase drive type capable of minimizing and preventing generation of the potential recess under the gap between the first transfer electrode and the second transfer electrode, thereby to be able to transfer the signal charge with a high transfer efficiency in any of a low voltage drive and a high voltage drive, and a method for manufacturing the same.
The above and other objects of the present invention are achieved in accordance with the present invention by a charge transfer device comprising:
a plurality of first transfer electrodes located with predetermined intervals, formed on a surface of a first insulator film formed on a semiconductor layer of a first conductivity type formed on a principal surface of a semiconductor substrate;
a second insulator film formed on the semiconductor layer of the first conductivity type between each pair of adjacent first transfer electrodes;
a third insulator film formed to cover a top surface and a side surface of each of the first transfer electrodes; and
a plurality of second transfer electrodes each formed on the second insulator film between each pair of adjacent first transfer electrodes and having opposite ends to partially overlap an adjacent end of the pair of adjacent first transfer electrodes,
the semiconductor layer of the first conductivity type including a first semiconductor region of a second conductivity type opposite to the first conductivity type, formed in self alignment, directly under each of the first transfer electrodes and the third insulator film formed to cover the side surface of the first transfer electrode, and a second semiconductor region of the second conductivity type formed, in self alignment, directly under the second insulator film between each pair of adjacent first transfer electrodes, the second semiconductor region having an impurity concentration higher than that of the first semiconductor region.
Here, the semiconductor layer of the first conductivity type can be constituted of a well of the first conductivity type formed at a surface of a semiconductor substrate of the second conductivity type, or of a semiconductor substrate of the first conductivity type.
In addition, a first transfer electrode pair composed of one first transfer electrode and one adjacent second transfer electrode and a second transfer electrode pair composed of one first transfer electrode and one adjacent second transfer electrode, are alternately located, and are driven with a first transfer clock and a second transfer clock opposite to each other in phase, respectively.
In one embodiment, the first semiconductor region of the second conductivity type formed directly under the first transfer electrode extends under the second insulator film on which there is located the second transfer electrode which cooperates the first transfer electrode to form the first transfer electrode pair. In this embodiment, the first semiconductor region extends under the second insulator film by a distance in the range of 0.5 times to 2.0 times of a thickness of the second insulator film.
In another embodiment, the second semiconductor region has a third semiconductor region formed at least one end of the second semiconductor region, in conjunction with the second semiconductor region, the third semiconductor region having an impurity concentration higher than that of the first semiconductor region but lower than the second semiconductor region. In this embodiment, the third semiconductor region has a size in the range of 0.5 times to 2.0 times of a thickness of the second insulator film.
In still another embodiment, the second semiconductor region has a third semiconductor region and a fourth semiconductor region formed at opposite ends of the second semiconductor region, respectively, in conjunction with the second semiconductor region, each of the third semiconductor region and the fourth semiconductor region having an impurity concentration higher than that of the first semiconductor region but lower than the second semiconductor region, but the third semiconductor region and the fourth semiconductor region being different from each other in at least one of the impurity concentration and the size. In this embodiment, each of the third semiconductor region and the fourth semiconductor region has a size in the range of 0.5 times to 2.0 times of a thickness of the second insulator film.
According to another aspect of the present invention, there is provided a method for manufacturing a charge transfer device comprising the steps:
preparing a semiconductor substrate having a semiconductor layer of a first conductivity type formed on a principal surface thereof;
forming a first semiconductor region of a second conductivity type opposite to the first conductivity type, in the semiconductor layer of the first conductivity type;
forming a first insulator film to cover the first semiconductor region of the second conductivity type;
forming a plurality of first transfer electrodes on the first insulator film, with predetermined intervals;
removing the first insulator film which is not covered with the first transfer electrodes;
forming a second insulator film to cover the first semiconductor region of the second conductivity type between each pair of adjacent first transfer electrodes, and a third insulator film to cover a top surface and a side surface of each of the first transfer electrodes;
introducing an impurity of the second conductivity type into the first semiconductor region of the second conductivity type, using the first transfer electrodes and the third insulator film as a mask, to form a second semiconductor region of the second conductivity type; and
forming a plurality of second transfer electrodes each formed on the second insulator film on the second semiconductor region of the second conductivity type between each pair of adjacent first transfer electrodes and having opposite ends to partially overlap an adjacent end of the pair of adjacent first transfer electrodes.
In one embodiment, the ion implantation of the impurity of the second conductivity type is carried out at a desired incident angle inclined in a charge transfer direction so that the first semiconductor region of the second conductivity type remains to extend from under each of the first transfer electrodes and the third insulator film, to under the second insulator film on which there is located the second transfer electrode which cooperates the first transfer electrode to form a transfer electrode pair. In this embodiment, the first semiconductor region extends under the second insulator film by a distance in the range of 0.5 times to 2.0 times of a thickness of the second insulator film.
In another embodiment, the ion implantation of the impurity of the second conductivity type is carried out at a desired incident angle inclined in a charge transfer direction and at another desired incident angle inclined in a direction opposite to the charge transfer direction, so that a third semiconductor region and a fourth semiconductor region are formed at opposite ends of the second semiconductor region, respectively, in conjunction with the second semiconductor region. In this embodiment, each of the third semiconductor region and the fourth semiconductor region has a size in the range of 0.5 times to 2.0 times of a thickness of the second insulator film.
The semiconductor layer of the first conductivity type can be constituted of a well of the first conductivity type formed at a surface of a semiconductor substrate of the second conductivity type, or of a semiconductor substrate of the first conductivity type.
In addition, the second insulator film and the third insulator film can be formed in the same step. Alternatively, the second insulator film and the third insulator film can be formed of the same material.
With the above mentioned arrangement, since the second conductivity type semiconductor region having a low impurity concentration is formed in a self-alignment under the gap between the first transfer electrode and the second transfer electrode, the potential recess occurring under the gap can be minimized or prevented. Accordingly, the drive voltage can be lowered without lowering the transfer efficiency of the signal charge.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.